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| AD825 - 15V | * AD825 SPICE Macro-model
11/19/99, Rev. B * JCH / ADI Cent Apps * * Copyright 1999 by Analog Devices, Inc. * * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * * THIS MODEL ONLY WORKS FOR POWER SUPPLIES OF +/-15V. FOR POWER SUPPLIES OF * LOWER VALUE, USE THE AD825_5V PART. PARAMETERS FOR THIS MODEL MATCH THE * PARAMETERS SPECIFIED UNDER +/-15V CHARACTERIZATION ON THE DATA SHEET. * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | .SUBCKT AD825_15V 1 2 99 50 30 * * INPUT STAGE & POLE AT 245 MHZ * R3 5 50 725 R4 6 50 725 C2 5 6 0.3E-12 I1 99 4 1.0E-3 J1 5 2 4 JX J2 6 3 4 JX Cin1 1 0 3E-12 Cin2 2 0 3E-12 Ios 1 2 20p Vos 1 3 1mV * EREF1 98 97 99 0 0.5 EREF2 97 0 50 0 0.5 * * GAIN STAGE & POLE AT 5.1 KHZ * R5 9 98 6.5E6 C3 9 98 4.6p G1 98 9 5 6 9.2E-4 V2 99 8 2.3 V3 10 50 2.25 D1 9 8 DX D2 10 9 DX * * POLE AT 200 MHZ R9 23 98 1E6 C8 23 98 0.8E-15 G5 98 23 9 98 1E-6 * * OUTPUT STAGE * R15 29 40 16 R16 29 41 16 L1 29 31 6E-12 V6 31 30 0 G7 29 40 99 23 6.25E-2 G8 41 29 23 50 6.25E-2 V4 25 29 0.2 V5 29 26 0.2 D3 23 25 DX D4 26 23 DX Vt1 99 40 0 Vt2 41 50 0 * *SUPPLY CURRENT CORRECTION * ISY 99 50 5.5m Fo1 98 110 V6 1 Do1 110 111 dx Do2 112 110 dx Vi1 111 98 0 Vi2 98 112 0 Fsy1 0 99 Vt1 1 Fsy2 99 0 Vi1 1 Fsy3 50 0 Vt2 1 Fsy4 0 50 Vi2 1 * * MODELS USED * .MODEL JX PJF(BETA=1.1E-3 VTO=-2.000 IS=5E-12) .MODEL DX D(IS=1E-15) .ENDS |
| LM3886 | .SUBCKT LM3886 posin negin out
posrail negrail mute * IN+ IN- OUT VCC VEE MUTE * Q1 posrail posin N004 0 NPN I1 N004 negrail 0.25m Q2 posrail negin N003 0 NPN I2 N003 negrail 0.25m Q3 N011 N003 N010 0 PNP Q4 N011 N018 N012 0 NPN R1 N012 negrail 2.2k I3 N018 negrail 0.1m Q5 N017 N018 N024 0 NPN R2 N024 negrail 2.2k Q6 posrail N011 N018 0 NPN R3 N009 N010 1.1k R4 N009 N023 1.1k Q7 N017 N004 N023 0 PNP Q8 N017 N013 N016 0 PNP Q9 N011 N025 N019 0 PNP R5 N015 N016 4.7k R6 N015 N019 4.7k R7 N013 gndpin 10k D1 N025 gndpin D D2 gndpin N025 D R8 out N025 10k C1 out N017 10p I4 N026 negrail 1m Q10 posrail N017 N026 0 NPN Q11 N030 N026 N031 0 NPN R9 N031 negrail 800 Q12 N009 N008 N014 0 PNP Q13 N015 N022 N014 0 PNP I5 posrail N014 1m I6 N022 negrail 1m D3 N021 N022 D D4 N020 N021 D R10 posrail N020 1k D5 N007 N008 D D6 N006 N007 D R11 posrail N006 1k Q14 N008 gndpin N005 0 NPN R12 N005 N001 1k D7 N002 mute D D8 N001 N002 D D9 N032 N031 D R13 N034 negrail 150 Q15 out N032 N034 0 NPN Q16 out N034 N036 0 NPN R14 N036 negrail 0.45 Q17 N032 N030 out 0 PNP D10 N029 N030 D D11 N028 N029 D D12 N027 N028 D R15 N033 out 150 Q18 posrail N027 N033 0 NPN Q19 posrail N033 N035 0 NPN R16 N035 out 0.45 I7 posrail N027 2.5m .model D D .model NPN NPN .model PNP PNP .end lm3886 |
| LT1968 True RMS Converter | * Copyright ? Linear Technology
Corp. 01/09/2007. All rights reserved. * * Note 1: For greater numerical accuracy in transient simulation, decrease* the maximum simulation time step. * * Note 2: This is a simplified model with no shutdown functionality. * * Node List (same as IC): GND IN1 IN2 VOUT OUTRTN V+ .SUBCKT LTC1968 1 2 3 5 6 7 ISUP1 7 1 2.3E-3 GIN2 0 11 VALUE={0.001*ABS(V(10)/(V(5,6)+0.002)*MIN(V(5,6)*4.183+1E-6,ABS(V(10))))} RIN1 10 0 1E3 RIN2 11 13 1.5E5 DS1 13 0 DS CIN1 10 0 1.5E-11 DS3 12 31 DS RIN3 12 11 50 EOUT 20 0 VALUE={ABS(V(11))+0.002+V(6)} ROUT 5 20 1.25E4 COUT 5 6 8.7E-12 GIN1 0 10 22 33 0.001 RIN4 11 0 1E3 EVCC 31 0 VALUE={0.5*V(7,1)-0.750} CIN2 11 0 1E-11 CS1 33 1 8E-13 CS2 22 1 8E-13 DIN1 2 7 DIN DIN2 4 2 DIN DIN3 4 3 DIN DIN4 3 7 DIN RS1 22 2 2E3 RS2 33 3 2E3 RS3 22 33 1E8 .MODEL DIN D (IS=1E-13 RS=0 KF=0 XTI=0) .MODEL DS D (IS=1E-16 RS=0 KF=0 XTI=0) .ENDS LTC1968 |
| AD744 | .SUBCKT AD744_2 11 14 10 16 13
12 15 *COPYRIGHT OF ANALOG DEVICES * AD744_2 SPICE Macro-model 3/91, Rev. B * JLW / PMI * Revision History: * Corrected VOS to be 0.1mV * This version of the AD744_2 model simulates the typical * parameters that correspond to those in the device data * sheet. * Copyright 1991 by Analog Devices, Inc. * Refer to "README.DOC" file for License Statement. Use of this model * indicates your acceptance with the terms and provisions in the License Statement. * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | compensation * | | | | | / \ *subckt AD744_2 11 14 10 16 13 12 15 VOS 14 7 DC 0.1E-3 EC 8 0 (13,0) 1 C1 5 6 0.33E-12 GB 12 0 (15,0) 1.67E3 RD1 5 16 16E3 RD2 6 16 16E3 ISS 10 1 DC 100E-6 GCM 0 15 (0,1) 1.76E-9 GA 15 0 (6,5) 2.33E-3 CCE 12 15 0.001E-12 RE 1 0 2.5E6 RGM 15 0 1.76E3 VC 10 2 DC 2.8 VE 9 16 DC 2.8 RO1 12 13 25 CE 1 0 1E-12 RO2 0 12 30 RS1 1 3 5.77E3 RS2 1 4 5.77E3 CCI 15 12 40E-12 RP 16 10 8.5E3 J1 5 11 3 FET J2 6 7 4 FET DC 13 2 DIODE DE 9 13 DIODE DP 16 10 DIODE D1 8 12 DIODE D2 12 8 DIODE .MODEL DIODE D() .MODEL FET PJF(VTO=-1 BETA=1E-3 IS=30E-12) .ENDS |